1. Field of the Invention
The present invention pertains to computation of a power index that assists in lowering power consumption in a semiconductor integrated circuit.
2. Description of the Related Art
In recent years, power consumption in semiconductor integrated circuits has increased as semiconductor integrated circuits continue to become more integrated, larger, and faster. As a result, performance degradation and/or shorter life spans of semiconductor integrated circuits due to heat generated by the circuit itself have become problems. Solutions include accurate estimation of power consumption at a design phase and redesign of the circuit to reduce power consumption.
Simulation is commonly used to estimate power consumption. In a simulation, input patterns are fed to a semiconductor integrated circuit, circuit operation is simulated, and the number of transitions of signals is counted. The power consumed at one transition of a signal is multiplied by the number of transitions, and the sum for all the signals is calculated, thereby giving power consumption for the semiconductor integrated circuit.
Japanese Patent Application Laid-Open Publication No. 2001-056827 discloses a method of estimating power consumption in which throughput per unit time of a bus is set; a core having a desirable function is extracted from a database and selected as an element; a connection surface of a bus or a connection part of the bus to an element is configured to determine the connection relation between the bus and each of elements; and simulation is carried out. After the process time and element configuration are clarified, performance is analyzed to evaluate power consumption of selected elements.
International Publication Pamphlet No. 2007-037017 discloses a method to measure the number of operations of a characteristic signal at each interval where power consumption is analyzed, the characteristic signal designating an operation mode of a circuit block. Based on the number of operations measured, it is determined whether the number of operations of the circuit block is to be measured. Only when it is determined that the number of operations of the circuit block is to be measured, is the number of operations of the circuit block measured.
To reduce power consumption in a semiconductor integrated circuit, Japanese Patent Application Laid-Open Publication No. 2006-277332 discloses a method, where in a semiconductor integrated circuit including multiple central processing units (CPUs) connected to a network, frequencies of a first and second CPU are changed and the provision of a clock signal to the first CPU is controlled according to the processing status of the first and second CPUs.
To lower power consumption in a semiconductor integrated circuit, Japanese Patent Application Laid-Open Publication No. 2004-228417 discloses a method where the volume of data in a functional module of a semiconductor integrated circuit is measured, and a clock frequency, power supply voltage and substrate bias are controlled so that a ratio of performance to power consumption is maximized based on the result of the measurement.
According to the conventional techniques above, when improvements in power consumption are conducted based on an estimation of power consumption, it is difficult to identify which module in a circuit is electrically problematic. A person who conducts power improvement work is not the designer of the circuit and thus typically, does not know the behavior of the circuit in detail.
Therefore, it is difficult to identify a module that is wasting significant power and to decide properly which part of a circuit should be reviewed, based on an estimation of power consumption. Conventionally, to improve power consumption, a process of trial and error is repeatedly performed for the modules in descending order of estimated power consumption.
However, a module that consumes significant power is not necessarily a module that wastes significant power. As a result, a worker has to check a circuit repeatedly retracing processes, whereby the workload and time involved in improving power consumption increase and the design time for a circuit becomes protracted.
Under such circumstances, a new technique that enables objective identification of a power wasting module even without detailed knowledge about circuit behavior is desirable.